Deliverables

4	GDSII and LVS Spice netlist, behavioral, synthesis, and 
LEF models, and extensive user documentation.

4	Integration support to ensure 
a successful tape out (included 
in standard design license fee).

Multi Phase DLL

Features

4	Designed for high-speed interface applications.

4	Generates precise multi-phase clocks directly from the reference clock.

4	Delivers optimal jitter 
performance over a wide 
frequency range.

Specifications
Part No. TCI-TN16FFPGLLVT-MPHDLL

- Reference frequency range 	1.2GHz - 6GHz
- Output phase delay equation	D(i) = i/*Tref
- Number of output phases	16
- Output phase separation	6.25% output cycle
- Output phase accuracy	+/-2.5% output cycle @ 6GHz
- Output duty cycle (nom, tol)	50%, +/-2.5%
- Input-to-output jitter (P-P) (max)	NDA Required

- Power dissipation (nom)	NDA Required
- Reset pulse width (min)	1µs
- Lock time (min allowed)	NDA Required
- Area (max)	NDA Required

- Added core supply package pins	1 VDD and 1 VSS
- Low freq. supply noise est. (P-P) (max)	+/-5% VDD
- Low freq. sub. noise est. (P-P) (max)	+/-5% VDD
- Reference input jitter (period, P-P) (max)	NDA Required
- Reference input duty-cycle range	NDA Required
- Reference input 10%-90% edge time (max)	150ps
- Slave output loading (max)	200fF

- Process technology	TSMC CLN16FF+GL 16nm
- Supply voltage (nom, tol)	0.8V, +/-10%
- Junction temperature (nom, min, max)	70C, -40C, 125C
*	Jitter numbers are worst-case estimates with 10% VDD supply and 
substrate noise—actual results will be better.