Deliverables

4	GDSII and LVS Spice netlist, behavioral, synthesis, and 
LEF models, and extensive user documentation.

4	Integration support to ensure 
a successful tape out (included 
in standard design license fee).

Ultra PLL

Features

4	New state-of-the-art architecture using high-speed digital and analog circuits that offers unprecedented operating ranges and extremely high performance.

4	Ultra low jitter performance for the most demanding SerDes and ADC reference clocks.

4	Ultra wide frequency range with multiplication factors over 250,000 to support 32KHz to 1GHz references.

4	Precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution.

4	Optional spread spectrum support with programmable rate and depth to meet tight FCC requirements.

4	Highly programmable so one PLL can be used for all applications on a SoC.

Specifications
Part No. TCI-TN40ULPOD-ULHPLL

- Divided reference frequency range	10KHz - 750MHz
- Total output frequency range	7.32KHz - 3GHz
- /1 output frequency range	15MHz - 3GHz
- Reference divider values	1-4096
- Integer feedback divider values	1-262144 (1-2^18)
- Fractional feedback divider bits (min)	26 (10 precise)
- Output divider values	1-2048
- Number of output phases	2
- Output phase separation	50% output cycle
- Output phase accuracy	+/-2.5% output cycle @ 3GHz
- /1 output multiples of div. reference	1-262144
- Bandwidth adjustment ratio	1:2^32
- Feedback signal delay (max)	n/a (FB internal)
- Output duty cycle (nom, tol)	50%, +/-1%
- Static phase error (max)	n/a
- Period jitter (P-P) (max)	NDA Required
- Long-term jitter (RMS) (max)	NDA Required

- Power dissipation (nom)	NDA Required
- Reset pulse width (min)	5µs
- Reset /1 output frequency range	~3GHz if enabled
- Lock time (min allowed)	NDA Required
- Freq. overshoot (max)	NDA Required
- Area (including isolation) (max)	NDA Required

- Number of PLL supply pkg. pins	1 VDDA, 1 VSSA (preferred)
- Low freq. supply noise est. (P-P) (max)	10% VDDA
- Low freq. sub. noise est. (P-P) (max)	10% VDDA
- Reference input jitter (long-term, P-P) (max)	NDA Required
- Reference input spread-spectrum modulation	NDA Required
- Reference H/L pulse width (min)	NDA Required
- Synchronous bypass included	Yes

- Process technology	TSMC CLN40ULP 40nm
- Supply voltage (VDD, VDDA) (nom, tol)	1.1V, +/-10%
- Junction temperature (nom, min, max)	70C, -40C, 125C
*	Jitter numbers are worst-case estimates with 10% VDDA supply and 
substrate noise—actual results will be better.